1. Field of the Invention
The present invention relates to an inverted groove structure for use in association with dielectrically isolated devices which allows two or more independently active devices that share a common terminal to be formed in a single, area-saving, dielectrically isolated (DI) island, or tub. The groove, or grooves, extend upward from the bottom of the island towards the common diffusion region so as to cut off the conductive channel between the active devices.
2. Description of the Prior Art
Integrated semiconductor structures were first fabricated using PN junction isolation in order to electrically isolate various active devices from each other. Such a structure usually has a substrate of one conductivity type and regions of opposite conductivity type located in the substrate and biased with respect to the substrate in a manner to utilize the PN junctions between the substrate and these regions as a form of electrical isolation. Other techniques were subsequently developed for isolating devices in an integrated circuit structure. One of these techniques includes the concept of dielectric isolation. In this technique of isolation, the various semiconductor devices are formed in "pockets", of tubs, of semiconductor material wherein the tubs are isolated from an underlying substrate, and also from each other, by means of a dielectric layer of material, usually of silicon dioxide. For many applications, this technique is preferable over PN junction isolation. For example, in the case of high voltage integrated circuits, the dielectric layer reduces the area overhead associated with device isolation, that is, the additional semiconductor material needed to support, without breakdown, the electric field of a reverse biased isolating junction. Also, dielectric isolation is well-suited for high speed integrated circuits, since this type of isolation avoids the added delays associated with charge redistribution in the depletion region of a reverse biased isolating junction that would otherwise occur as a result of voltage level changes during circuit operation.
A basic description of the dielectric isolation technique can be found in U.S. Pat. No. 3,579,391 issued to J. L. Buie on May 18, 1971. Here, the method of producing dielectric isolation for one or more regions in the substrate includes the steps of cutting a groove in a semiconductor wafer surrounding the region to be isolated, establishing an insulating layer on the surface of the wafer and on all surfaces of the groove, and providing mechanical supporting substrate material to fill the groove. Later work in this area developed a structure wherein a V-shaped groove was used in the process described above. U.S. Pat. Nos. 3,913,124 and 3,956,033 issued to D. K. Roberson on Oct. 14, 1975 and May 11, 1976, respectively, describe both a V-groove dielectrically isolated structure and method of forming the same. As disclosed, the V-groove structure is formed by masking and anisotropically etching the monocrystalline substrate. After depositing a layer of silicon dioxide, silicon nitride, or other dielectric material, the groove is filled with mechanical supporting material. A problem with this V-groove isolation technique, however, is that a separate dielectrically isolated island, or tub, is needed for each independently active device of the circuit, even if many of these devices share a common terminal and thus could conceivably share a common diffusion region. U.S. Pat. No. 4,467,344 issued to G. Chang et al on Aug. 21, 1984 discloses a technique for achieving area reduction in a dielectrically isolated circuit by forming two devices which share a common terminal in the same DI tub. In particular, two gated diode switches are formed in a single tub and isolated from one another by a high resistance JFET channel formed between a deep n diffusion extending down from the top surface of the tub and a second such diffusion extending up from the floor of the tub. Although this technique allows for devices to be combined in a single tub, additional masking and diffusion steps must be added to the device fabrication process to form the high resistance JFET channel.
Therefore, a need remains for a technique of combining active devices, which share at least one common terminal, in a single DI tub which is fairly simple in implementation and will not significantly alter the device fabrication process.